Current Research Areas
Extreme Temperature Electronics
Moon equatorial regions experience wide temperature swings from -180°C to +130°C during the lunar day/night cycle, and the sustained temperature at the shadowed regions of lunar poles can be as low as -230°C. Mars diurnal temperature changes from about -120°C to +20°C. All exploration endeavors operating on the Moon or Mars surface will need electronics that are able to survive and operate in a wide temperature range. In addition, applications like engine control and drill monitoring require digital controllers that can sustain over 300°C. Although novel materials like SiGe and SiC are able to function under such extreme temperatures, the clocked synchronous circuits tend to fail due to the large transistor switching speed variations. This research is to design delay-insensitive asynchronous circuits that are able to operate reliably under such wide temperature swings.
Radiation Hardened Digital System
Electronics for space and nuclear environment applications are concerned with radiation effects such as, Single Event Transients (SETs), Single Event Upsets (SEUs) and Single Event Latchups (SELs). Radiation-hardening by design techniques such as Triple Modular Redundancy (TMR) and Error Detection and Correction (EDAC) have their vulnerabilities. This research is to develop a design methodology utilizing delay-insensitive asynchronous logic to improve SEU/SEL mitigation and reduce area overhead. The achievements to-date include single- and two-bit SEU mitigation, as well as SEL mitigation without data loss during power cyclings.
The impact of software viruses has been felt by the entire computerized world. Hardware, on the other hand, was considered safe and attack-free. However, as technologies advance and markets expand, hardware is becoming vulnerable like software. Malicious logic could be inserted into a circuit like a Trojan horse such that it lies dormant and is very difficult to detect until activated, but then cannot be effectively defeated. This research is to develop a methodology and software tool to model the potential threats/attacks of a given digital system, and to search for and mitigate malicious logic inserted.
A prototype hardware threat modeling/analysis tool, TRUTH, is now available for download from here.
Radio Frequency Identification (RFID) allows common objects to have individual identities, memory, processing capabilities, and the ability to communicate and sense, monitor, and control their own behaviors. Individually and integrated, all these technologies can provide huge benefits to society. But they also pose new threats to rights, privacy of individuals, and security of organizations. This research is to design hardware for RFID readers and tags to mitigate the potential attacks, improve the system security, and enable the transfer-of-ownership capability.
Side-Channel Attack Mitigation
In contrast to invasive attacks to digital ICs, side-channel attacks do not require the target to be physically de-packaged. Instead, attackers can monitor the fluctuations of certain external parameters such as power consumption and timing delay caused by different data being processed. The recorded data will be analyzed to calculate the desired information. This research is to develop a power-/timing-attack mitigation technique by designing delay-insensitive asynchronous digital ICs. Developed techniques include Dual-spacer Dual-rail Delay-insensitive asynchronous Logic (D3L), Multi-Threshold D3L (MTD3L), and Delay-Insensitive Ternary Logic (DITL) to balance the power consumption and obfuscate the timing delays among different data patterns.
Ultra-Low Power Digital Circuit
Ultra-low power circuitry has profound impacts on many applications. Among all ultra-low power techniques, Multi-Threshold CMOS (MTCMOS) is very attractive for reducing sub-threshold leakage current during standby mode because existing designs can be easily converted into MTCMOS versions. This research aims to solve the three major problems of the MTCMOS technology applied to the prevailing synchronous systems – “sleep-transistor” sizing, storage element data loss, and sleep signal generation – by utilizing delay-insensitive asynchronous logic. The developed Multi-Threshold NCL (MTNCL) methodology has shown significant area reduction, energy savings, and compatibility with industry IC design flow.
Asynchronous Cell Matrix
One exciting anticipated outcome of nanotechnology is the ability to construct systems with many orders of magnitude more components. This truly remarkable expansion of physical hardware must be met by innovation in computing architecture. Cell Matrix, developed by Cell Matrix Corp., is a construction of physically homogeneous, reconfigurable hardware components, which are connected in a regular structure topology and configured to implement a desired digital circuit. This architecture could be used to implement dynamic, massively parallel, self-modifying/-repairing/-healing circuits. However, the current synchronous Cell Matrix requires clocks, which are not feasible for extremely large systems. This area is to develop a dynamically fault-tolerant asynchronous Cell Matrix without any clocks, which is able to reconfigure itself in response to faulty components and changing requirements.
NSF CCLI Phase II – Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer
The development of synchronous circuits currently dominates the semiconductor design industry. However, there are major limiting factors to the synchronous, clocked approach, including the increasing difficulty of clock distribution, increasing clock rates, decreasing feature size, increasing power consumption, timing closure effort, and difficulty with design reuse. Asynchronous (clockless) circuits require less power, generate less noise, produce less electro-magnetic interference (EMI), and allow for easier reuse of components, compared to their synchronous counterparts, without compromising performance. As the demand continues for designs with higher performance, higher complexity, and decreased feature size, asynchronous paradigms will become more widely used in the industry, as evidenced by the 2003 International Technology Roadmap for Semiconductors’ (ITRS) prediction of a likely shift from synchronous to asynchronous design styles in order to increase circuit robustness, decrease power, and alleviate many clock-related issues. The 2005 ITRS predicts that asynchronous circuits will account for 19% of chip area within the next 5 years, and 30% of chip area within the next 10 years. Therefore it is extremely important for Computer Engineering students to be introduced to asynchronous paradigms to make them more marketable and more prepared for the challenges faced by the digital design community for years to come.